Freescale Semiconductor /MKL28T7_CORE1 /FTFA_FlashConfig /FOPT

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Interpret as FOPT

7 43 0 0 00 0 0 0 0 0 0 0 0 (00)LPBOOT0 0 (00)BOOTPIN_OPT 0 (00)NMI_DIS 0 (00)RESET_PIN_CFG 0 (00)LPBOOT1 0 (00)FAST_INIT 0 (00)BOOTSRC_SEL

BOOTSRC_SEL=00, NMI_DIS=00, BOOTPIN_OPT=00, RESET_PIN_CFG=00, FAST_INIT=00, LPBOOT0=00, LPBOOT1=00

Description

Non-volatile Flash Option Register

Fields

LPBOOT0

no description available

0 (00): Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1.

1 (01): Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1.

BOOTPIN_OPT

no description available

0 (00): Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin

1 (01): Boot source configured by FOPT (BOOTSRC_SEL) bits

NMI_DIS

no description available

0 (00): NMI interrupts are always blocked

1 (01): NMI_b pin/interrupts reset default to enabled

RESET_PIN_CFG

no description available

0 (00): RESET pin is disabled following a POR and cannot be enabled as reset function

1 (01): RESET_b pin is dedicated

LPBOOT1

no description available

0 (00): Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1.

1 (01): Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1.

FAST_INIT

no description available

0 (00): Slower initialization

1 (01): Fast Initialization

BOOTSRC_SEL

Boot source selection

0 (00): Boot from Flash

2 (10): Boot from ROM

3 (11): Boot from ROM

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